The 4567 performs Video Matrix Fetches, during displayed video times,
in all of the original VIC-II modes (SCM, MCM, ECM, BMM) . This is true for
both 40 and 80 column (320 and 640 pixel) modes. During VMF, the 4567 reads
both banks (A & B) of memory over both data busses D0-D7 and E0-E7. The D0-D7
bus provides the video matrix data, E0-E3 provides color data, and E4-E7
provides character attribute data.
CDF -- Character Data Fetch
The 4567 performs Character Data Fetches immediately after each Video
Matrix Fetch in the original VIC-II modes except bitmap mode. During this fetch
Character image data is fetched from ROM or RAM bank A over the D0-D7 bus.
BMF -- BitMap Fetch
The 4567 performs Bitmap Data Fetches immediately after each video
Matrix Fetch, only in the bitmap mode. During this fetch, Bitmap image data
is fetched from RAM bank A over the D0-D7 bus.
BPF -- Bitplane Fetch
The 4567 can perform Bitplane image fetches during displayed video
times, if the Bitplane mode (BPM) is enabled. The number and position of these
fetches is determined by which bitplanes are enabled. During bitplane fetches,
even numbered bitplane data is fetched over DO-D7 and odd numbered bitplane
data is fetched over E0-E7.
RF -- RAM refresh
The 4567 performs six cycles of dynamic RAM refresh every scanned video
line. During this time no data is fetched and CASA* and CASB* are not activated.
SPF -- Sprite Pointer Fetch
Up to eight Sprite Pointer Fetches can occur each scanned video line.
One SPF is generated for each sprite that is enabled and currently being
displayed. During an SPF, the pointer to the sprite image data is fetched
from the video matrix area of memory for the sprite in question over the
D0-D7 data bus.
SDF -- Sprite Data Fetch
Three Sprite Data Fetches follow each Sprite Pointer Fetch. During
this time, sprite image data for the sprite in question is fetched over
the D0-D7 data bus.
DAT -- Display Address Translation
Display Address Translation, or DAT fetches, are not actually DMA-type
accesses, but rather CPU address redirections to RAM. In this case, the
unmultiplexed address bus is totally separated from the multiplexed address bus.
COL -- Color RAM accesses
Color RAM is also accessed by the CPU via an address translation. This
is because color RAM would otherwise be located in the I/O area.