System Specification for C65: C65 System Hardware - The CSG 4510 Microcontroller Chip (cont.)

System Specification for C65

Fred Bowen

March 1, 1991

2.3.5.6 FAST SERIAL MODE

The EAST SERIAL logic consists of a 2-bit write-only register, which resides in location 0001 (hex). This register may only, be accessed by the CPU if neither the AEC or DMA/ line is low. Upon reset, both bits in the register are forced low which allows the device to operate as normal (the CNTA, SPA, PRC57 and FLAGA/ lines will not be affected).

Bit 7 of the FAST SERIAL register is the Fast Serial Mode disable bit (DMODE* bit).

Bit 6 of the FAST SERIAL register is the FSDIR* bit. When the DMODE* bit is set high, the FSDIR* bit will be used as an output to control the fast serial data direction buffer hardware, and as an input to sense a fast disk enable signal. This function will affect the CNTA, SPA, PRC57 and FLAGA/ lines as summarized in the following table.

DMODE*	FSDIR*	FUNCTION
0	0	Fast Serial mode is disabled.
x	1	Both the FLAGA/ and the PRC57 lines will behave as outputs. The FLAGA/ output will reflect the state of the CNTA pin, whereas the PRC57 output will reflect the state of the SPA pin.
1	0	Both the CNTA and SPA lines will behave as outputs. The CNTA ouput will reflect the state of the FLAGA/ pin, whereas the SPA output will reflect that of the PRC57 pin.

This page has been created by Sami Rautiainen.
Read the small print.	Last updated August 10, 2001.