System Specification for C65: C65 System Hardware - The CSG 4510 Microcontroller Chip (cont.)

System Specification for C65

Fred Bowen

March 1, 1991

PSYNC 29 OUT This output line is provided to identify those cycles in which the microprocessor is doing an OP CODE fetch. The ?SYNC line goes high during PH1 of an OP CODE fetch and stays high for the remainder of that cycle. If ABC or DMA/ is low during the rising edge of PH1,in which pulse PSYNC went high, the processor will stop in its current state and will remain in the state until either AEC or DMA/ goes high. In this manner, the SYNC signal can be used to control either the AEC or DMA/ line to cause single instruction execution.

AEC 30 IN This input signal is the Address Enable Control line. When high, the address bus, R/W are valid. When low, the address bus, R/W and MAP/ are in a high-impedance state except for A17, A18 and A19 each of which will be connected to the A16 line.

DMA/ 31 IN This signal is connected to a 3K passive pullup. When this signal is low the address bus and R/W will be tri-stated. This will allow external DMA devices to assume control of the system bus lines.

(READY) Internal Signal This signal is generated internally via the AEC and DMA/ lines. The READY signal goes high when both AEC and DMA/ are high. It goes low if either ABC or DMA/ goes low. The READY signal allows the user to single-cycle the microprocessor on all cycles including write cycles. A low state on either DMA/ or AEC during the rising transition of phase one (PHI) will deassert the READY line and halt the microprocessor with the output address lines holding the current address. This feature allows micro processor interfacing with low speed memory as well as fast (max 2 cycle) Direct Memory Access (DMA).

IO/ 32 IN This input signal is used to select the internal registers of the device, provided memory is not being mapped by the CPU.

MAP/ 33 OUT This signal is passively pulled-up (3 Kohm) whenever DMA/ or AEC is pulled low. This output signal is used to indicate whether or not-memory is being mapped by the device. If the CPU is addressing a mapped memory region the MAP/ line will go low and will inhibit the 10/ line from selecting an internal register If the CPU is not mapping memory the MAP/ line will be high and A16-A19 will be kept low.

This page has been created by Sami Rautiainen.
Read the small print.	Last updated August 10, 2001.

PSYNC	29	OUT	This output line is provided to identify those cycles in which the microprocessor is doing an OP CODE fetch. The ?SYNC line goes high during PH1 of an OP CODE fetch and stays high for the remainder of that cycle. If ABC or DMA/ is low during the rising edge of PH1,in which pulse PSYNC went high, the processor will stop in its current state and will remain in the state until either AEC or DMA/ goes high. In this manner, the SYNC signal can be used to control either the AEC or DMA/ line to cause single instruction execution.
AEC	30	IN	This input signal is the Address Enable Control line. When high, the address bus, R/W are valid. When low, the address bus, R/W and MAP/ are in a high-impedance state except for A17, A18 and A19 each of which will be connected to the A16 line.
DMA/	31	IN	This signal is connected to a 3K passive pullup. When this signal is low the address bus and R/W will be tri-stated. This will allow external DMA devices to assume control of the system bus lines.
(READY)	Internal Signal		This signal is generated internally via the AEC and DMA/ lines. The READY signal goes high when both AEC and DMA/ are high. It goes low if either ABC or DMA/ goes low. The READY signal allows the user to single-cycle the microprocessor on all cycles including write cycles. A low state on either DMA/ or AEC during the rising transition of phase one (PHI) will deassert the READY line and halt the microprocessor with the output address lines holding the current address. This feature allows micro processor interfacing with low speed memory as well as fast (max 2 cycle) Direct Memory Access (DMA).
IO/	32	IN	This input signal is used to select the internal registers of the device, provided memory is not being mapped by the CPU.
MAP/	33	OUT	This signal is passively pulled-up (3 Kohm) whenever DMA/ or AEC is pulled low. This output signal is used to indicate whether or not-memory is being mapped by the device. If the CPU is addressing a mapped memory region the MAP/ line will go low and will inhibit the 10/ line from selecting an internal register If the CPU is not mapping memory the MAP/ line will be high and A16-A19 will be kept low.